You are not logged in.

#1 2014-12-01 00:40:09

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

WARNING: TLDR, skip to post #13100 below or your brain might explode!
__________________________________________________________________________________________

”gamba2” wrote:

Our attempts to clone DayStar PDS adapters have been abandoned.

I've long thought that this project needs revisiting, so this is an attempt to clean up the drivel I've posted on Mac68k.info and ASK FOR HELP!

The following post amounts to an informal compilation of observations:

--Regarding other PowerCache Adapters and their their lack of intervening Logic in adaptating a PDS for compatibility with the IIci Cache Slot.
--Notations about missing, contradictory a/o possibly remotely relevant information in the DevNotes  and documentation in the Apple Press pubs.
--Inferences (WAGs) drawn from noted differences between PowerCache Adapter revisions for the IIsi.
--That the Vampire Video implementations in IIci, IIsi, the VRAM enabled SE/30 and the rat's nest of early MoBo Video implementatio seems the most likely culprit.

------ Most of this probably needs to be condensed into a table relating Address Mapping, Pseudo-Slot I.D./interrupt considerations contrasted with the Physical Slot implementations of the various Macs making up what I feel is a relevant sampling.

From Cloning the Daystar PDS Adapter for the SE/30

ISTR techknight telling me that the adaptation moves the memory addressing of the SE/30 PDS to another part of the memory map where the IIci Cache Card resides. I don't know how that works, but something of the sort has been done before.

I'm taking my usual fumble-fingered stab at developing a ridiculous multifunction card for the SE/30. So of course, I'm looking to make provisions for hanging as much crap off the thing as is humanly/technically possible, interrupt permitting.*** Rearranging the PDS signals to match the IIci Cache card I can crib from DCaDftMF. If the lines for the memory displacement PAL are identified by someone who has an adapter card, I can easily add pads/thru-holes for it to hold in reserve along with the remapped, but unpopulated EuroDin120 connection for such a time as the PAL programming project might be accomplished. Obviously that would need to be done by others. roll

Thanks to mcdermd, I've got a 16MHz PowerCache "accelerator" that I'd dearly love to stick on top of that sucker. There may be no clock rate enhancement, but I figure Daystar wouldn't have marketed this card if "merely" adding cache didn't give give the 16MHz Mac II series a serious kick in the pants, just as the Cache Card does for the IIci at its native 25MHz clock rate.

Is it possible to jumper additional interrupt lines from wherever appropriate in the GLUE/NuChip architecture of the SE/30 and its IIcx sire which might then be addressable by an SE/30 with the IIfx ROM SIMM or a hacked variant thereof on board? I've already got plans for jumpering at least 10 lines to the RidiculousCard from the SE/30 MoBo, so WTH? tongue

”bbraun" wrote:

I'm not familiar with the more advanced bus arbitration signals of the 030, but the PDS and the cache card don't have a dedicated address space. They're on the processor bus. They're whatever addresses they choose to respond to.

Hrmmm? Thanks for that bit of info. All the adaptations for the SE/30 on gamba show only two cards with the adapter. I wonder which interrupt the Cache slot uses, could that be the hitch? ***

I mentioned this to trag and he said that someone will have to do this eventually. Might as well get started! wink

DCaDftMF p.384
"If you are determined to design an expansion card other than a cache memory card, you should be aware of the following limitations.
- power  .  .  .
- device opening  .  .  .
- The absence of some machine specific signals imposes severe restrictions restrictions on your design.

I'm guessing that  .  .  .

IF:

LCIII PDS has no PLD on board and three interrupt lines available . . .

LCIII DevNote:
/SLOTIRQ.C Slot $C interrupt request. Not supported by the Macintosh LC III.
/SLOTIRQ.D Slot $D interrupt request. Not supported by the Macintosh LC III.
/SLOTIRQ.E Slot $E interrupt request. Generates an interrupt corresponding to a device in NuBus slot $E.

SLOT $E = SE/30 Video
IRQ 4/SLOT $C = unused in SE/30 (as opposed to +not supported+)
IRQ 5/SLOT $D = unused in SE/30 (as opposed to +not supported+)

<  drivel alert  >

THEN:

WAG = PowerCache requires an IRQ line

No IRQ line available on IIci Cache Slot

WAG: IIci = No gots Slot $E but the LCIII does, the SE/30 uses Slot $E for Video.

PLD remaps Slot $E to the unused IRQ in the gamba diagrams?

<  /drivel alert  >

GAH! that doesn't even make sense to me now! Table fixed below?

IRQ 1/SLOT $9 = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 2/SLOT $A = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 3/SLOT $B = available on SE/30 PDS & NuBus Slot in IIcx
IRQ 4/SLOT $C = unused in SE/30 (as opposed to not supported )
IRQ 5/SLOT $D = unused in SE/30 (as opposed to not supported )
SLOT $E = SE/30 Video

IIci Video addresses in Slot $0, but "memory addresses in $B of NuBus address space?"  Full Quote Below

IIci Devnote shows no interrupts available in Cache Slot, which differs from DCaDftMF

Pin C26 = n.c. in DevNote = IPL0 in DCaDftMF
Pin C25 = n.c. in DevNote = IPL1 in DCaDftMF
Pin C12 = n.c. in DevNote = IPL2 in DCaDftMF

IPL0-2 would be the only interrupts common to all three: SE/30 PDS, LCIII PDS and the IIci Cache Slot, which has no IRQ lines available . . .

The Mac II adapter has no adaptation on it, plugging directly into CPU and PMMU IIRC. I'll assume that the socketed PowerCache accelerators needed no adaptation either, having access to every CPU signal in the same manner.

I'm tired and confused again, I've probably mangled numbers and letters, but my gut tells me there has to be something in there somewhere that sheds at least the tiniest bit of light on the function of the CPLD adaptation . . .

”bbraun" wrote:

So, I'm confused on what slots or interrupts have to do with a cache card.
The whole point of a cache card, I thought, is when the CPU does a read operation (from a cacheable address), the cache can return it to the CPU faster, and hopefully burst transfer the entire cache line, than RAM ordinarily would. That's it. There's no driver that talks to a NuBus Slot, the cache card doesn't do anything to trigger a host processor interrupt (and corresponding OS software handling).

I don't know what it has to do with a cache card, but an accelerator in the IIci cache slot is probably a whole different kettle of worms. The PowerCache works in the IIci cache slot and in the LCIII PDS @ $E without a hitch. Only the lines have been changed to protect signal integrity and a few SMT doo-dads stuck on here or there for good measure on the LCIII adapters.

But in the SE/30 you need the CPLD (i think that's what trag called it) on the adapter, the line conditioning doo-dads as well as the signal switcharoo and $E just happens to be the slot address of the SE/30's video subsystem.

My hunch is that this is more than coincidental. Maybe yes, maybe no, but that's the one clue I've got so far and I'm stickin' with it!

I tried to find the roadmap pic of PowerCache adaptation for the various Macintosh models and it didn't turn up.

___________

I think I may have figured out the source of confusion. In GttMFH2e, pp.389-392 list the signals available on the IIci cache slot. The bolded entries are signals Apple placed on the connector for diagnostics purposes only and would be the jumping off point for those "determined to design an expansion card other than a cache memory card," such as the PowerCache accelerators.

My theory is that something about Daystar's implementation using machine level interrupts /IPL0-IPL2 or some other "extraneous" signals available for operations "other than cache" puts a hurt on the function of cards at location $E that are not designed to operate within the framework of the Slot Manager operations. The video subsystem of the SE/30 may appear to occupy $E to Sot Manager, but there was no reason for Apple to operate within its own Slot Manager design guidelines for a "card" in a slot location in the SE/30 that's unimplemented in hardware.

My theory is that operations of the PowerCache accelerator interfere only with those operations of slot $E that fall outside standard Slot Manager Design guidelines. Slot $E would therefore be fully functional in six slot Macs and the LCIII PDS that fall within those standard Slot Manager operations . . .

...but well and truly bork the SE/30's video subsystem, hence, the CPLD adaptation?

__________

/NUBUS - In the Macintosh SE/30, indicates address in the memory range $6000 0000 to $FFFF FFFF. This signal is active when the CPU addresses the built-in video display. (Expansion cards can use this signal and further decode the slot address ranges to avoid conflict with the video logic.

Sounds like a right fine application for a CPLD to me. Dunno, whatchathink?

__________

Two last clues(?) identified, one of them noted previously but documented here with confirmations and one new observation supporting my theory statement.

Quote, GttMFH2e p.412___________________________________________________________

Pseudo-slot video in the Macintosh IIci
Like the built-in video in the Macintosh SE/30, the video interface in the Macintosh IIci simulates some features of a Macintosh II Video Card in a NuBus expansion slot. By simulating the features of an expansion card in a slot, the Macintosh IIci can share common System ROM with the other Macintosh models that use the MC68030 processor. This simulation of a video card in a NuBus slot is called pseudo-slot video.

The video screen buffer in the Macintosh IIci occupies memory starting at $0000_0000 in physical address space. Using the memory management unit in the MC68030, the Macintosh IIci maps the screen buffer to logical address space starting at $FB000_0000. That address space was chosen because it is the same as the address space used by expansion slot $B in the six-slot in the six-slot models of the Macintosh II family.
________________________________________________________________________________

That $B was an intentional choice in the IIci design jibes with the above tidbit about operations of the PowerCache Accelerators and my guess that they step all over Interrupt/Slot/Pseudo-Slot assignments of the IIsi and SE/30.

Driving the video subsystems of either appears to me to require some kind of logical intervention to sidestep Slot Manager operations as well as the memory mapping issue techknight had previously noted.

The second discovery would be the existence of two versions of the Twin-Slot Adapter for the IIsi.

Rev1(?) http://www.applefritter.com/node/20222
Rev2(?) (c)1992 http://www.applefritter.com/files/image … -10199.jpg

Hopefully the differences between the two versions will shed some light on the Cloning Project requirements for someone competent. My guess is that later (read faster better, more likely to wind up in a IIsi/SE/30) PowerCache Cards had on-board ROM and circuitry mods circumventing the need for the drastic interventions necessary for compatibility with previous models found on the earlier adapter.

I'll also guess that the location of the last remaining IC and pin assignments at U1 on the simplified Rev.2 adapter will be crucial in reverse engineering.

WAG: the unimplemented pads at U3 on the Rev.2 adapter suggest to me the possibility that a Rev.1.5 version was produced with backward compatibility with earlier PowerCache models, possibly another crucial tidbit? < edit: buzzing pin assignments here too might be crucial >

Dunno, I think I've done about all that I can at this point. I don't have any of the adapters linked here and I've never even seen the SE/30 adapter which puts me at a severe disadvantage. Pics would be greatly appreciated, posting them in the NuBus Mafia project on 'fritter would seem to be the most useful for later iterations of the cloning project.

I'll get the lead out and post pics there of the LCIII adapter myself, or have someone competent post them for me! wink

__________

Forgot to mention the part about the PowerCache driving the IIsi and SE/30 video subsystems being the root cause of said slot assignment and memory mapping gymnastics. **

__________

** I wrapped that last bit back around to the top, hopefully it makes more sense that way.

Last edited by jt (2016-11-27 18:15:28)

Offline

#2 2014-12-01 00:48:10

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

GAH! That's the second time I've done something to get a "Document Expired" error!

At any rate I hope the above makes more sense than the Mac68k thread  .  .  .  likely not. hmm

Help requested:

-- High Res Pics of that gen.1 IIsi Adapter in the 'fritter link.
-- Any pics at all of the SE/30 Adapter for the PDS
-- Any pics at all or confirmation of the existence of the (inferred) gen.1.5 IIsi Adapter with the IC implemented at U3.

-- Buzzed connections of any and all above.

-- TattleTech NuBus/PDS report from SE/30 with both PDS and Socketed Adaptations for the PowerCache.


Interpretation of the drivel above by anyone with a clue?

Offline

#3 2014-12-01 04:03:37

macdrone
Member
From: Rainier, Or
Registered: 2014-05-25
Posts: 235

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

I wish I had a clue, but I get most of what you are saying (just have no idea how to help).

I will follow closely as an 040 in a SE30 would be sweet.

Offline

#4 2014-12-01 04:43:33

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Me too and thanks! I'm glad you got any of what I was trying to get at, that's an auspicious beginning for one of my threads! smile

Offline

#5 2014-12-11 00:29:47

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

It's my quarter-weekly Wednesday crash day and I've been moping around the place in true holiday spirits, but I did come up with what might be an interesting angle of investigation of my Slot $E Borkage Theory.

Might putting one of my Futura II/Ethernet Daughtercard combos in Slot $E of a six slot Mac give any indication of what kind of further addressing might be needed for the SE/30's NuBus Signal and the straight up $E PseudoSlot Video implementation? Such would be a convenient example of an additional, discrete functions operating within the Vidcard's $E physical location and PseudoSlot space?

Apple Press Pub quote of currently unremembered origin from above: __________________________________________________________

/NUBUS - In the Macintosh SE/30, indicates address in the memory range $6000 0000 to $FFFF FFFF. This signal is active when the CPU addresses the built-in video display. (Expansion cards can use this signal and further decode the slot address ranges to avoid conflict with the video logic.

Offline

#6 2014-12-11 02:23:12

bbraun
Member
Registered: 2014-05-29
Posts: 1,064
Website

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

What are you trying to do?
The Daystar PDS Adapter as I understand it functionally adapts the IIci cache cards to the 030 PDS.  It also has some other bells and whistles that don't seem particularly attention-worthy.  FPU and 32k cache are pretty normal.  So are you just trying to figure out how to adapt IIci cache cards to 030 PDS for use in the SE/30 like the artmix adapter?

What help are you looking for?
I'm not clear what you're asking for.


You linked to the same thing twice there.

Forgot to mention the part about the PowerCache driving the IIsi and SE/30 video subsystems being the root cause of said slot assignment and memory mapping gymnastics. **
__________

** I wrapped that last bit back around to the top, hopefully it makes more sense that way.

There are several products called PowerCache, but none of them I'm aware of exist in the address space, and do not drive a video subsystem and do not conflict with Slot E.  Is there any technical reason you believe it does?  AFAICT, you've got a very long chain of speculation going, all of which is predicated on anecdotes.  Are you sure you aren't confusing nubus on SE/30 with IIci cache card on SE/30?

Offline

#7 2014-12-11 04:30:24

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

bbraun wrote:

What are you trying to do?
The Daystar PDS Adapter as I understand it functionally adapts the IIci cache cards to the 030 PDS.  It also has some other bells and whistles that don't seem particularly attention-worthy.  FPU and 32k cache are pretty normal.

Yes, it adapts the signal line mismatch, but the SE/30 (assumption, I've never seen a picture of one) the IIsi and Artmix adapters all require active component intervention to do so. However, the DayStar adapter has no active components on board for the LCIII Slot E -> IIci Cache Slot conversion, only the pin/signal reassignments and some line conditioning are required for that adapter.

bbraun wrote:

So are you just trying to figure out how to adapt IIci cache cards to 030 PDS for use in the SE/30 like the artmix adapter?

Exactly! gamba and co. gave up on that project.  I mentioned "clean room cloning" of the IIsi adapter to trag in PM. He said it was probably something "someone" would need to do eventually.

bbraun wrote:

You linked to the same thing twice there.

oopsie: http://www.applefritter.com/node/10199  .  .  .  on further examination, the double-linked card's not even a PowerCache adapter! roll


bbraun wrote:
jt wrote:

Forgot to mention the part about the PowerCache driving the IIsi and SE/30 video subsystems being the root cause of said slot assignment and memory mapping gymnastics. **

There are several products called PowerCache, but none of them I'm aware of exist in the address space, and do not drive a video subsystem and do not conflict with Slot E  .  .  .

I meant to say "driving the Video subsystems haywire" or something of the sort. "Borking" or "interfering with" would be a great substitutes for "driving" in that sentence. Sorry for the confusing .TXT

bbraun wrote:

Is there any technical reason you believe it does?

Yep, I don't think the PowerCache accelerators interfere with any conventional implementation of Slot E. I think that Apple's implementation of the SE/30's Video System at PseudoSlot $E is anything but conventional. Why would Apple's engineers feel any need to work within the confines of Slot Manager guidelines to implement video in a "Slot" that won't exist in hardware? I don't think they did and I think that's the problem DayStar needed to address with active components these adapters and not on others.

bbraun wrote:

Are you sure you aren't confusing nubus on SE/30 with IIci cache card on SE/30?

Absolutely certain, different issues entirely. NuBus on SE/30 is a set of black boxes: the ICs and ASIC that need to be connected. That would be to each other, the SE/30's PDS and likely jumpered to the MoBo if I follow the Mac IIx architecture adapted from the Mac II schematic. Project30 (NuBus in SE/30) is unconnected to the cloning project, other than the PCB passing the PDS signals to a (proposed) PowerCache adapter clone at the top of the card.

I'm passing the PDS up to the top of the card and out of its side to begin with anyway. If (more likely when) I can't get NuBus up and running in the SE/30, I'll have the layout done for a multiple slot PDS expansion card. The passthru traces will be implemented as fully as possible on the etched sides of the wire-wrap protoboard I'm designing.

bbraun wrote:

AFAICT, you've got a very long chain of speculation going, all of which is predicated on anecdotes.

It's meant to be a list of the items I've found in the documentation that might be germane, or not. The comparisons I've made between my Daystar LCIII adapters and the IIsi adapter pics on 'fritter stand. This led me to look into the matter of the difference I noted and I turned up discrepancies in the Docs along with what I think might be clues as to what's done in the circuitry on the SE/30(?) and IIsi adapter that isn't required on my LCIII adapter.

bbraun wrote:

What help are you looking for?
I'm not clear what you're asking for.

I'm not exactly looking for help, I'm beyond help when it comes to this kind of thing. I'm really just trying to get the ball rolling.

Pictures of a DayStar SE/30 PDS adapter would be great, if any? I surmise it may have been a socket only factory conversion from comments I've read? Pictures of any other adapters having active circuitry, or not, would be a great help. My sample size leaves much to be desired.

I'll try to post pics of the LCIII adapter for comparison tomorrow.

Thank you very much for taking a look. I really hope this makes at least a little bit of sense to you now. hmm

Last edited by jt (2014-12-11 05:00:44)

Offline

#8 2014-12-11 05:10:23

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Heh! I knew I'd found a pic of another IIsi Adapter. wink

http://www.applefritter.com/node/20334

Has anyone got a link to the "Family Tree" illustration of DayStar's PowerCache Cards and Adapters?

Offline

#9 2016-11-27 17:20:53

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

”gamba2” wrote:

Our attempts to clone DayStar PDS adapters have been abandoned.

I've long thought that this project needs revisiting, so this is an attempt to clean up the drivel I've posted on Mac68k.info (see above) and ASK FOR HELP!

______________________________________________________________________________


First off, I finally found Daystar's family tree of PowerCache Adapters:

ViBPwx.jpg

Can anyone ID any of the adapter/machine matchups from this diagram?


Here's the second (earlier or later?) single IC DualPort IIsi PowerCache adapter implementation of the IIsi TwinSlot adapter below:

daystar_dual_port-20334.jpg

edit: found a far better pic of what seems to be the adapter above:

Credit: AppleFritter.NuBus Mafia
dq9AlW.jpg


Here's my best reference to the IIsi (and by extension SE/30) TwinSlot PowerCache adaptation:

Credit: applefritter
iisi_pds_adapter-10199.jpg

My goal here is to finish the Gamba2 adapter cloning project.

I think my next step will be be mapping the traces on the four surface/subsurface layers visible on this board in Illustrator. My brain works visually, so let's see if I can identify as many of that active IC's pin assignments as possible to create the (Greek to me) schematic that other brain's thought processes interpret so well. This should provide some good clues as to the identity/function of the mystery IC under that "1400" label.

__________________________________________________________________________


Again, this project could mistakenly be described a clean room reverse engineering of the function of the IC Artmix achieved for their SE/30 board from what's likely the same data available for that successful project. It's actually an extension of the Gamba2 project relevant to cloning as many of DayStar DIGITAL's PowerCache adapters as possible, beginning with the IIsi adapter and then modifying for the SE/30.

This project would be just the first step in that endeavor. It's also an important adjunct to my pet Project 30. As the goal is to clone the IIsi TwinSlot PowerCache adapter, it might differ significantly from the SE/30 PowerCache adapter. Complications resulting from differences between available interrupts (actual slot assignments) and the PseudoSlot ID assignments of Video implementations in different Macs appear to me to be the crucial differentiation reflected in circuitry present in the various adapters in the family tree diagram above.

Last edited by jt (2016-11-27 20:51:28)

Offline

#10 2016-11-28 04:19:00

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Rummaged around on the Quicksilver today and found a pic of an IC (hopefully) like the one on the TwinSlot Adapter above:

pRkJJp.jpg

Of course the pad for the small IC on the other end of this TwinSlot card is populated  .  .  .
.  .  .  with a sticker covered IC!  roll



edit: Surprise, surprise, surprise! </Gomer>

It's a PAL from TI 20L8-10CFN

TIBPAL20L8-10CFN Datasheet - sort of, gotta hate these specsheet hijacking outfits. mad

Last edited by jt (2016-12-03 14:20:56)

Offline

#11 2016-12-03 14:25:57

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Results so far from: Are there Chips on your PowerCache Adapter?

AFAIK, every Mac that has an implementation of Slot ID $E in any form except the LCIII and IIci require active adapters.

IIci doesn't count because its implementation of cache memory space (possibly NuBus SuperSlot memory space is involved?) and $E implemented in NuBus are compatible by (definition) design.

LCIII is a special case because its PDS is an oddball hardware implementation of a full '030 PDS connector at Slot ID $E. Installation of the PowerCache adapter in its PDS precludes any other use of $E, hence no possible conflict and its passive adapter.

Members of the Mac II series have NuBus implemented in Slots $9-$E. The IIci is an oddball, with slots $C-$E implemented in NuBus.

IIcx follows the pattern of its big brother the IIx, implementing the first of its three NuBus slots at $9-$B. No implementation of Slot ID $E is made as a physical slot or a pseudoslot in its design. No possible conflict there means only a passive adapter is required for the PowerCache.

Last edited by jt (2016-12-03 14:27:09)

Offline

#12 2016-12-03 14:55:36

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

As an aside, the IIci really is an odd duck:

--only of the Mac II series to bump its NuBus Slots up into $C-$E range, bypassing $9-B implemented in Macs II,IIx and IIcx

--IIci Video located in $0, the home base for the Mac in its standard memory map, but Video Memory is mapped to Slot ID $B *****

I'm curious about the Video Slot ID/Video Memory two step of the IIci:

At first blush it seems to me that placing Video Memory at $B either makes room for it or places it out of contention with main system memory access? Having it located in the $B space also puts it out of contention with memory addressing from NuBus access in slots $C-$E.

ISTR reading that NuBus was "chunked" three slots at a time, which makes some sense to me in looking at various implementations.

Question: does it make sense to anyone else to see IIci system memory in chunk $0, video memory in chunk $9-$B and NuBus in chunk $C-$E? Might it have to do with some kind of "branching" of the CPU and I/O interrupt/interrupt level setup?

The Cache Card is located in memory at $5200 000 - $52FF FFFF so I'm lost, where the f**k is that?!!!! roll

*****GttMFH2e p.410

Offline

#13 2016-12-08 18:54:29

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Really interesting project, I wish I were more knowledgeable.  My musings...

I looked at the difference between the cache slot in the IIci and the pds slot on the SE/30.  Most of the connector signals are present on both slots, but the cache slot is missing several that are on the pds slot:

1a. Reserved 1b. Reserved 1c. PWROFF
2a. Reserved 2c. /NUBUS
3a. /BUSLOCK 3b. /TM1A  3c. /TMOA
4a. /IRQ3  4b. /IRQ2 4c. /IRQ1
38b. ECLK 38c. C16M

Conversely, these are misssing on the pds slot:
5c. /CFLUSH
13c. /CENABLE
32a. /ROMOE
36b. CPUDIS
40b. CACHE

I am curious if the active adapters use any of those signals.  Are they wired to the PAL?
If not, what pins are wired to the PAL?  Looking at pictures of the artmix card,  it looks like besides power, only 3 or 4 lines are put through the logic array.  I've never used one, but there exists inexpensive 16 channel logic analyzers, I wonder if that would give an idea of what's happening.   Further, has anyone attempted to read the logic from the artmix or daystar cards, or are they known to be protected?  Way above my abilities here, just pondering...


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#14 2016-12-08 20:43:09

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Without ever actually seeing one, I'm absolutely sure the "read fuse" is blown on the Artmix board's PAL is blown. IIRC, the gentleman who did that work patented his method. Dunno, but out of respect and admiration for his work, I'll be upset if anyone tries to reverse engineer his solution.

I've never actually seen an ACTIVE PowerCache adapter of any kind IRL, but I'm guessing they're PALs are all read-proofed as well. It wouldn't surprise me a bit if Logic Probing the single PAL on the (latest rev?) IIsi adapter might have been involved in the Artmix development process. Even if so, I'm maintaing a "clean room" cloning process regarding the Artmix board.

Dunno, the only time I've ever been involved in Logic Probing was the late 80's and it was my partner who did the electron pushing and digital reverse engineering for that project. I remain blissfully ignorant of such technicalities, I was the idea guy, coming up with the original invention and the visually oriented breakdown that finally led to decrypting/reverse engineering the target machine's Font format. smile

Continuing this gamba project is fun in itself, but for me it's really an icing on the cake adjunct to Project 30.

Last edited by jt (2016-12-08 20:46:41)

Offline

#15 2016-12-10 05:36:34

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

jt wrote:

Even if so, I'm maintaing a "clean room" cloning process regarding the Artmix board.

Fair enough, and surely more satisfying when you reach your goal!


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#16 2016-12-10 05:55:55

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

MicroMac and Diimo also made PDS-Cache adapters.  All very similar to the last rev. Daystar and Artmix boards.  I would hazard a guess they all use the same logic manipulation.

micromac_cache.png

diimo_cache.png


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#17 2016-12-10 17:23:30

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Thanks so much for your input, I'd not seen either of one of those. They do look like the PowerCache/Artmix single chip implementations.

I did find one made by DayStar, but it has two ICs, appears to be for the IIsi and be plugged into the extreme danger zone:

Dd3uZW.jpg

Since the thruholes for what would normally be the IIsi's Cache Slot for the accelerator are unpopulated, it may actually be installed correctly for use in the SE/30. That leads me to think that the smaller IC might be there to remap the slots' pin assignments to enable a single PCB to be adaptable to either IIsi OR SE/30 configuration. Dunno, this guesswork is fun!

At this point I'll take any info I can get. Buzzing the connections of any of these boards would be very helpful. If the Artmix board is handy to anyone, just the pin assignments of the PAL indicating connections to pins on the PDS & Cache sides would be within the bounds of this project. As you say, they all do the same thing and comparing pinouts of all available would be fascinating to me, if more than likely redundant as you implied.

From your pic, it appears that MicroMac's accelerator had the FPU implemented on the Accelerator, making it the most simple PCB layout.

Offline

#18 2016-12-10 21:18:58

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Yeah, it seems the only pictures of them I could find were taken with an old Sony Mavica with some butter on the lens.  I can't interpret the part number from the PAL at all.  The Daystar card has a sticker on it, and of course, I couldn't find the solder side of that board either.  The Artmix card has some pretty high resolution pictures of it online, so I was able to see the part number for that example, GAL16V8D-15LP (data sheet).

Pin 1 - CLK
Pins 2-9 Input
Pin 10 GND
Pin 11 /OE
Pins 12-19 I/O
Pin 20 - VCC

Easiest thing to check first is if Pin1 on that PAL is connected to PDS 38A or 38C.  That would at least confirm the timing source.

Last edited by joethezombie (2016-12-10 21:20:37)


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#19 2016-12-10 23:09:18

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Oh my!  It does look like it's plugged into the danger zone.  LOL.  I think you are right about that PCB being adaptable.  For sure that is the SE/30 adapter adaptation (ha!).  It looks to read SE/30 OR SECONDARY S1 in the upper left corner.  Plus it matches the advertisement: 2406671347_48595e7c7f_b.jpg


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#20 2016-12-11 04:16:34

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Great info there, this is really nice for a change! I usually wind up only talking to myself in these threads. neutral


edit: just noticed that adapter is advertised for use with an '040 accelerator. That neatly explains the adapter's lack of an FPU socket.

Last edited by jt (2016-12-11 04:19:28)

Offline

#21 2016-12-12 18:38:24

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Had quick feedback from BadGoldEagle over at 68kMLA. He posted this pic of the Socked version of the PowerCache for the SE/30.

9107747564_4591a19e6e_b.jpg

It looks very much like there may be a PAL located between PMMU (built into the 68030) and the Cache ICs*** at U22. It may be looking like the Socketed PowerCache has the same kind of memory address/Slot ID issues as the Universal PowerCache does in the the IIsi/SE/30 PDS.

Further food for thought! smile


*** ATT7C174J-15 - CACHE-TAG RAM, 8KX8, 28 Pin, Plastic, SOJ

Last edited by jt (2016-12-12 18:44:32)

Offline

#22 2016-12-16 14:01:24

LCGuy
Administrator
From: Sydney, Australia
Registered: 2014-05-13
Posts: 816

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

I hope he pulls/has pulled that Maxell bomb! yikes

Offline

#23 2017-01-24 19:10:12

joethezombie
Member
From: Idaho
Registered: 2015-08-20
Posts: 20

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

joethezombie wrote:

... The Artmix card has some pretty high resolution pictures of it online, so I was able to see the part number for that example, GAL16V8D-15LP (data sheet).

Pin 1 - CLK
Pins 2-9 Input
Pin 10 GND
Pin 11 /OE
Pins 12-19 I/O
Pin 20 - VCC

Easiest thing to check first is if Pin1 on that PAL is connected to PDS 38A or 38C.  That would at least confirm the timing source.

So I was thinking about this again, and here are some more thoughts:

So if you look closely at the photos posted on Flickr, we can make out the traces of the active component.

The top right pin looks to go through a resistor, then to the PDS connector A38, which is the CPUCLK signal.  My guess the signal is too "hot" to go directly to the active chip, so it passes through a resistor firstly.  But more importantly, it lets us know the orientation of the chip, so that pin 1 is the top right (on the solder side) of that picture.

The next pin down (#2), we can follow the trace again to the PDS connector A7, which is STERM.

Pin #3 goes up to the danger zone, and branches off to a few locations. A10 on the PDS passthrough, and B29 on the CACHE slot.  Those are both BGACK.  It also goes to a resistor, but I can't see what that resistor is connected to.

Pins 4-10 look unconnected, but the data sheet shows pin 10 as ground.

Moving to the other side, bottom left (pin11) looks unconnected.

Pin 12 leads to the PDS connector A10, which is again BGACK.
Pin 13 leads to the bottom jumper. That jumper is closed, but I don't know what it goes to.
Pins 14 and 15 look unconnected.
Pin 16 goes through a resistor, then up to the CACHE slot, A38 which is the CPUCLK.
Pin 17 goes through a resistor, then up to the-- and I am guessing here, because of the black tape on the picture,but I would assume that trace won't cross the other traces on the same plane-- anyway, up to the PDS passthrough slot, A38 which is also CPUCLK!
Pin 18 goes up under the tape again, but I will assume stays to the far right and connects with the CACHE slot, C2, which is STERM.
Pin 19 looks unconnected.
Pin 20 looks unconnected, but according to the data sheet, it must be +5V VCC.

So, to theorize, the only signals these active cards manipulate is CPUCLK, BGACK, and STERM.

EDIT:  I found this link about 68K Bus arbitration.  I think this is exactly what these active cards are doing, acting as a state machine and controlling the clock to the connected devices.

Last edited by joethezombie (2017-01-25 00:10:24)


Apple: ][+, //c, IIgs, 128K, SE, SE/30, IIfx, IIsi, Q700, MacTV, 6100 DOS, 8100/110, G3 AiO, ANS700/200,G4 DP500
Commodore: 64, 128D, Amiga 3000

Offline

#24 2017-01-28 06:38:07

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

Thank heaven, somebody is helping out! I'll take a look tomorrow, it's time for bed. Just spent about an hour of quality time with the vacuum de-soldering gun. wink

Offline

#25 2017-01-28 15:30:40

jt
Member
From: Bermuda Triangle, NC USA
Registered: 2014-05-21
Posts: 1,407

Re: Cloning the Daystar PDS Adapters for the IIsi and SE/30 - Take 2

THX very much! That bus arbitration link is just the kind of thing I need, not only for this project, but for adapting the IIsi NuBus card to the SE/30 as well. Research lines are most definitely on a convergent path for these two projects, gotta love it!

Did I post this link over here yet? TheByte article: How the Macintosh II NuBus Works is crucial to my getting a handle on the IIsi NuBus in SE/30 problem.

NuBus and PDS are handled in much the same way by Slot Manager, as are PseudoSlot implementations. The SE/30's video implementation at Slot$E appears to pose just such a bus arbitration issue with Cache operations of the Daystar Accelerator as described in your link:

David Lie on March 01, 1998 at 11:39:44:

: I'm a bit confused by how this could work. The way I see it
: is:

: 1) When any device wants the bus it pulls BRn low.
: 2) The CPU returns BGn low regardless of the state of
: BGACKn.
: 3) When BGACKn floats high, the device with the token
: pulls it low and releases BRn.
: 4) The CPU then releases BGn.

: Can multiple devices request the bus? If one device
: requested it and didn't get it before another device
: earlier on the chain requests it, isn't it possible
: that both will get BG's and simultaneously go for the
: bus when it becomes free? On the other hand, if
: only one device is allowed to request at a time,
: why the extra BGACK signal?

: -DL


When multiple devices are used on the bus, you have to
do something more sophisticated than simply connecting
both to the common BR and BG lines. (Yes, it is possible
that they both request the bus at the same time, and
that is why BGACK is needed.)

The daisy chain, as discussed in lecture, is one possible
solution. Instead of each device seeing the SAME BG signal,
the real one is seen only by the first device. This device
forwards a modified BG to the next device, and so on.
If a device sees its incoming BG signal, then it may
grab the bus if it wants to. If so, the outgoing BG signal
is turned off. If not, then the outgoing BG signal is
a copy of the incoming BG signal.

The question I think you are asking concerns when a device
late in the chain requests the bus by asserting BR, and the
processor responds by asserting BG. This BG would propagate
along the chain because nobody else wanted the bus. Now,
if suddenly one of the earlier devices requests the bus, it
immediately sees BG asserted and assumes it controls the bus.
Meanwhile, the BG signal has propagated to the original
requestor, which now also assumes that it can have the bus.

I believe that for a reasonable number of devices, the BG
propagation would be sufficiently rapid that all devices
would see some version of this signal in a single bus clock
cycle. If each device was controlled by a state machine
controlled by this clock, the problem described above could
never occur. In that example, either the original requestor
would see BG in one cycle and the other device would request
the bus during the next... at which point the original requestor
has already taken control of the bus. Or, the 'other' device
requests at the same time that BG is asserted by the
processor, sees that BG is asserted, grabs the bus, and
deasserts its outgoing BG signal... the original requestor
will then have to wait until the bus is free again.

Hope this helps...

Maybe it's better to describe it as the accelerator's cache accesses contending with the video subsystem for control of the bus for the same $E location.

This jibes well with my theory on Macs with and without active adaptation for the PowerCache being dependent upon implementation of Slot $E.

Much food for thought here. I've gotta get a printer up and running, I can't access the Byte article at work to print it ore read it there. hmm

Hey, mcd! Any chance you could host that .pdf?

BTW: thanks much for your donation of the Mac II Adapter to the cause. I just discovered how great that PowerCache card you included with it was. I'd thought it was a 16MHz card from reading the clock speed suffix on the 68881, never looked at the fine print on Proc or crystal can. 50MHz is da BOMBE! big_smile




Has anyone heard from bbraun? I've not seen him post and he didn't respond to an email I sent asking how he was doing. I'm getting very worried about him.

Last edited by jt (2017-01-28 15:44:22)

Offline

Board footer

About ThinkClassic

ThinkClassic specialises in the maintenance, repair, restoration and modification of Vintage Apple and Macintosh computers. Ask questions and find answers about classic Apple desktops, laptops, accessories and peripherals.